93d2ff782f
The main motivation for this change is to: (a) add missing CPU flags
(including those flags that provide mitigation for the recent CVE flaws)
as 'traits'; and (b) adjust and clean up the layout of the 'hw/cpu/'
directory.
To that end, the following are the set of changes in this patch.
(*) Introduce a new cpu/x86 directory; and vendor-specific files: amd.py
and intel.py; with __init__.py containing the *common* stuff:
- hw/cpu/x86/amd.py -- AMD-only traits.
- hw/cpu/x86/intel.py -- Intel-only traits.
- hw/cpu/x86/__init__.py -- Common traits for both AMD and Intel.
- hw/cpu/x86.py -- Two things: (a) move the contents of this file
into x86/__init__.py, which is its new location; this move
preserves the integrity of the string trait names and Python
paths, as they were before; and (b) given point (a), remove the
now no longer needed hw/cpu/x86.py. (Justification: We are
removing this file to maintain consistency with the way it's done
througout the 'os-traits' repository.)
- hw/cpu/amd.py -- Deprecate the contents of this file with a
comment; and copy them into hw/cpu/x86/amd.py, which is its new
location.
Comparison between the old and the new layouts of os_traits/hw/cpu/:
Old Layout New Layout
---------- ----------
cpu/ cpu/
├── aarch64.py ├── aarch64.py
├── amd.py ├── amd.py [DEPRECATED]
├── __init__.py ├── __init__.py
└── x86.py └── x86/
├── amd.py
├── __init__.py
└── intel.py
(*) Add various missing CPU flags to x86/intel.py, x86/amd.py and to
x86/__intel__.py.
(*) Copy, and deprecate with a comment, flags from cpu/x86.py, i.e..
"VMX" (Intel) and "SVM" (AMD), into corresponding vendor-specific
files.
References
----------
[1] Thread start:
http://lists.openstack.org/pipermail/openstack-discuss/2019-May/006281.html
-- On reporting CPU flags that provide mitiation (to CVE flaws) as
Nova 'traits'
[2] Thread conclusion:
http://lists.openstack.org/pipermail/openstack-discuss/2019-May/006364.html
Closes-Bug: #1830948
Change-Id: I1c9a72d19ef9dadfb931efa3894867099974bcc7
Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com>
86 lines
2.9 KiB
Python
86 lines
2.9 KiB
Python
# -*- coding: utf-8 -*-
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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TRAITS = [
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# ref: https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions
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'AVX',
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'AVX2',
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'CLMUL',
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'FMA3',
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'FMA4',
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'F16C',
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'MMX',
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'SSE',
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'SSE2',
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'SSE3',
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'SSSE3',
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'SSE41',
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'SSE42',
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'SSE4A',
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'XOP',
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'3DNOW',
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# ref: https://en.wikipedia.org/wiki/AVX-512
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'AVX512F', # foundation
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'AVX512CD', # conflict detection
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'AVX512PF', # prefetch
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'AVX512ER', # exponential + reciprocal
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'AVX512VL', # vector length extensions
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'AVX512BW', # byte + word
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'AVX512DQ', # double word + quad word
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# ref: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets
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'ABM',
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'BMI',
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'BMI2',
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'TBM',
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# ref: https://en.wikipedia.org/wiki/AES_instruction_set
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'AESNI',
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# ref: https://en.wikipedia.org/wiki/Intel_SHA_extensions
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'SHA',
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# ref: https://en.wikipedia.org/wiki/Intel_MPX
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'MPX',
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# ref: https://en.wikipedia.org/wiki/Software_Guard_Extensions
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'SGX',
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# ref:
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# https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions
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'TSX',
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# ref: https://en.wikipedia.org/wiki/Advanced_Synchronization_Facility
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'ASF',
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# ref: https://en.wikipedia.org/wiki/VT-x
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# NOTE(kchamart): The 'VMX' trait is Intel-only, and does not belong
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# in this file (which is supposed to be a "common" file for all
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# x86-related). But we need to retain it here forever to not cause
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# Placement breakage.
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'VMX',
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# ref: https://en.wikipedia.org/wiki/AMD-V
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# NOTE(kchamart): The 'SVM' trait is AMD-only, and does not belong
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# in this "common" file. But we need to retain it here forever to
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# not cause Placement breakage.
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'SVM',
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# ref: https://git.qemu.org/?p=qemu.git;a=blob;f=docs/qemu-cpu-models.texi
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# Recommended to allow guest OS to use 1 GB size memory pages. Not
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# included by default in any of the Intel and AMD CPU models. So
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# this should be explicitly turned on for all Intel and AMD CPU
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# models.
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'PDPE1GB',
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# ref: https://git.qemu.org/?p=qemu.git;a=blob;f=docs/qemu-cpu-models.texi
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# Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in
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# some operating systems. This flag must be explicitly turned on
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# for *all* Intel and AMD CPU models. (Prerequisite: host CPU
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# microcode needs to support this feature before it can be used for
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# guest CPUs).
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'STIBP',
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]
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