Caio Felipe Cruz 5c8c4bfe3a ice: fix DPLL pin handling for SMA/UFL pins
This change resolves incorrect DPLL pin handling when configuring SMA
software pins and improves synchronization between PTP and DPLL
subsystems.

Test Plan:

PASS: Package builds correctly. Build of the modules succeeds for std
and rt.
PASS: Build ISO and install.
PASS: Check if DPLL pin mapping is correct.

Story: 2011456
Task: 52714

Change-Id: Idb86a99ccfa6f428b19b761c034d81342f80cad5
Signed-off-by: Caio Felipe Cruz <caio.soaresdacruz@windriver.com>
2025-10-03 15:03:22 -04:00
2023-08-31 01:36:50 +00:00
2023-04-28 12:38:51 -04:00
2024-03-01 19:24:03 -03:00
Description
StarlingX Linux kernel
12 MiB
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